Intricate signal processing of real world analog signals often requires signal conversion into the digital domain. Conversion makes feasible the use of either conventional digital computers or special purpose digital signal processors. Applications for such processing include wireless communications, such as portable voice, data, and messaging systems that generally employ digital receivers to process transmitted complex high frequency RF signals. The receivers typically acquire the RF analog signals in the gigahertz frequency range and translate the signals to lower intermediate frequencies, or IFs. Thereafter, the low IF signals are digitized and processed through digital signal processing components and techniques.
One technique for achieving high resolution of relatively low frequency signals with lower precision components utilizes oversampling or sigma-delta modulation followed by digital low pass filtering and decimation. Oversampling refers to operation of the modulator at a rate many times above the Nyquist rate, which is typically twice the bandwidth of the sampled analog signal. Modulators of the sigma-delta type are often implemented in high resolution applications because of the ability to shape noise away from the sampled signals. Moreover, sigma-delta modulators offer the distinct advantage of multi-bit resolution with a single bit output.
Normally, digital sigma delta converters are designed with internal bit widths greater than the input signal bit widths. The additional bits are employed to prevent signal overflow from occurring. However, should the input signals approach positive or negative full-scale, the additional overflow bits may be insufficient to prevent overflow. In such circumstances, the internal node is typically clamped at a value of 2N.times.full-scale to prevent 2's complement wraparound. Normally, the overflow clamp is implemented by determining if the carry-out of the two most-significant-bits have the same sign.
For signal processing applications utilizing a plurality of sigma delta modulators, the respective outputs may be fed as inputs to a digital scaler/summer. An example of a conventional digital scaler/summer is a derivative of a sigma delta based converter having one or more Pulse Density Modulated (PDM) single bit inputs. The inputs are appropriately scaled by respective values contained in respective N-bit wide input gain registers and added at a first summing node. Feedback signal values of +/-full-scale and +/-twice full-scale are added to the first summing node and a second summing node and scaled by a value contained in an M-bit wide feedback gain register. The gain of the signal is determined by the ratio of the M and N bit register values with a resulting output comprising a single bit PDM composite of the scaled input signals. A digital scaler/summer of this type is disclosed in U.S. Pat. No. 6,023,184, filed Sep. 16, 1997 issued Feb. 8, 2000, entitled "Converter Providing Digital Scaling and Mixing," and U.S. Pat. No. 5.999.114, filed Sep. 16, 1997 issued Dec. 7, 1999, entitled "Dithered Digital Gain Scaler/Summer," both of which are assigned to the assignee of the present invention and are incorporated herein by reference.
In the case of a digital gain scaler/summer, the technique for handling signal overflow is different than that for a typical sigma delta converter. This is because the feedback gain comprises a scalable value, freeing bits to accommodate overflow. Consequently, the number of overflow bits becomes a function of the feedback gain.
While at first glance the variation in overflow for conventional gain scaler/summers appears to add a level of flexibility and efficiency, the variation in the overflow bits can create a latency in the initiation of the clamp on the second integrator. This occurs when the number of bits reserved for overflow approaches the number of bits used to represent the feedback gain value. As a consequence of this latency, the output of the first integrator will follow the overdriven input until the feedback from the clamped output of the second integrator moderates its ascent. Thus, the state of the first integrator's output is a function of the initiation of the clamping on the second integrator's output. When the inputs of the gain scaler/summer return to a non-overdriven state, decaying transients or oscillations appear that are proportional to the output magnitude of the first integrator.
Therefore, what is needed and heretofore unavailable is a scalable overflow clamp for a gain scaler/summer that manages overflow to minimize oscillations as the scaler/summer returns to normal conditions from an overdriven state, by keeping the number of bits reserved for overflow a constant. The scalable overflow clamp and method satisfies this need.